This invention relates to programmable logic device integrated circuits (“PLDs”), and more particularly to circuitry on PLDs that can be used for receiving and/or transmitting high-speed serial data signals.
Shumarayev et al. U.S. patent application Ser. No. 11/256,346, filed Oct. 20, 2005 (hereinafter “the Shumarayev et al. reference”) shows and describes circuitry of the general type that is of interest in connection with the present invention. (It will be understood by those skilled in the art reading the Shumarayev et al. reference that the output of circuit element 26 is the clock input to circuit element 28, and that the output of circuit element 21 is the data input to circuit element 28 (although this last connection is not actually shown in FIG. 2 of Shumarayev et al.).
The Shumarayev et al. reference shows some respects in which high-speed serial data signal receiver circuitry on a PLD can be modularized so that the various modules in a cluster (“quad”) of such modules can be used either as clock and data recovery (“CDR”) circuitry or as clock management unit (“CMU”) circuitry. For example, if several channels of high-speed serial data are to be received and processed in a coordinated way, each high-speed serial data signal can be applied to a respective one of the modules in a quad that are operated as CDR circuitry, while a reference clock signal is applied to another module in the quad that is operated as CMU circuitry. The CMU module provides clock signals that may be needed by the other modules that are operating as CDR circuitry. Any module in a quad that is not needed for these operations can be operated as stand-alone CMU-type circuitry (e.g., for providing a regulated clock signal for use by other circuitry on the PLD).
The above basic idea of the Shumarayev et al. reference can be extended and/or augmented in various useful ways in accordance with the present invention.